The present invention relates to an improvement of a semiconductor memory provided with redundancy circuits.
Recently, high density integration of semiconductor memories has been proposed. Associated with the realization of high density integration is a decrease in manufacturing yield due to a defect in a semiconductor substrate or a defect of a memory cell which is caused in the manufacturing process. To help alleviate the above-mentioned situation, a method has been adopted whereby the defective part of the semiconductor memory is replaced by a redundancy circuit formed on the same chip.
FIG. 1 shows a modified form of an arrangement of an RAM provided with redundancy memory cells dislosed on pages 80 and 81 of the Report on the Feb. 18, 1981 Sessions of the ISSCC. In the arrangement of FIG. 1, the redundancy circuits of two rows are formed. Ordinarily, an address signal (eight bits, here) is input from a computer or the like (not shown) to a decoder 1, and the decoder 1 decodes this address signal and outputs it to a selecting circuit 3. The selecting circuit 3 comprises 256 (=2.sup.8) NAND gates 31-1 to 31-256 and inverters 33-1 to 33-256 which are respectively connected to the NAND gates 31-1 to 31-256. The selecting circuit 3 receives the decoded address signal and sets a voltage of the select line corresponding to the address signal among select lines 5-1 to 5-256 to the select level (H level, here). The select lines 5-1 to 5-256 are respectively connected to the inverters 33-1 to 33-256. In this way, the memory cells corresponding to the address signal are selected from memory cells 7-1 to 7-256.
Data is read out from or written in the selected memory cells through bit lines 9. At this time, a programmable control circuit 11 outputs a redundancy select signal so as not to select the memory cells for redundancy. FIG. 2 shows an example of the arrangement of the memory cells shown in FIG. 1. This memory cell comprises: n channel MOS transistors 43 and 45 whose gates are connected to a select line 41; a flip flop consisting of n-channel MOS transistors 47 and 49; and resistors 51 and 53. The data is written in and read out from this memory cell through bit lines 55 and 57.
For example, it is assumed that the defective memory cell was found in the memory cells 7-1 and the memory cells 7-1 are substituted by the redundancy memory cells 17-1. The programmable control circuit 11 is programmed so that the redundancy memory cells 17-1 are selected when the address signal designating the memory cells 7-1 is input. This programming is performed by cutting off the fuse elements in the programmable control circuit 11. When the address signal to designate the memory cells 7-1 including the defective memory cell is input, the programmable control circuit 11 outputs an H level redundancy select signals from output terminals A1/A1 to A8/A8 and H level redundancy enable signal from output terminal RE1 to a redundancy selecting circuit 13 in accordance with the programming.
This redundancy selecting circuit 13 is constituted by NAND gates 13-1 and 13-2, which each have 9 input terminals and inverters 13-3 and 13-4, similar to the selecting circuit 3. H level signals are applied to all of the input terminals of the NAND gates 13-1. The redundancy selecting circuit 13 sets a voltage of a select line 15-1 for redundancy to a select level (H level, here) in response to the select signal. Thus, memory cells 17-1 for redundancy are selected.
At the same time, the signal at L level indicating that the redundancy memory cells 17-1 were selected is output from a detecting circuit 21. The detecting circuit 21 comprises a NAND gate 21-1 connected to the output terminals of the NAND gates 13-1 and 13-2 and an inverter 21-2 connected to the output of this NAND gate 21-1. When the redundancy memory cells 17-1 are selected, the NAND gate 13-1 outputs a signal at L level. Due to this, the NAND gate 21-1 outputs a signal at H level. The inverter 21-2 outputs a signal at L level. This L-level signal is input to the NAND gates 31-1 to 31-256.
Therefore, when the redundancy memory cells 17-1 are selected, the NAND gates 31-1 to 31-256 of the selecting circuit 3 output signals at H level. Thus, the inverters 31-1 to 33-256 of the select circuit 3 output signals at the non-select level (L level, here). As a result, the ordinary memory cells 7-1 to 7-256 are not selected irrespective of the value of the address signal. Any of the ordinary memory cells 7-1 to 7-256, if found defective, are substituted by the memory cells 17-1 and 17-2.
In the conventional semiconductor memory device shown in FIG. 1, the detecting circuit 21 detects when the redundancy memory cells 17-1 were selected and outputs the corresponding signal. The selecting circuit 3 receives the output signal of the detecting circuit 21 and sets the ordinary memory cells 7-1 to 7-256 into the non-select state. Namely, voltages of the select lines 5-1 to 5-256 are set to a non-select level (L level, here). Consequently, there is a fear such that both of the redundancy memory cells and ordinary memory cells are selected (double selection). To avoid the abovementioned problem, it is necessary to provide a difference between the time when the voltage of the select line for redundancy is set to H level and the time when the ordinary select line is set to H level. Namely, it is necessary to set the time when the redundancy select line is set to H level later than the time when the select line is set to H level. Due to this, it is difficult to realize the high-speed operation of the semiconductor memory device. In addition, the necessity of the detecting circuit 21 causes the circuit arrangement to become complicated and makes high density integration of the circuit difficult. Further, it is difficult to make the operation of this circuit fast due to the signal delay caused by this detecting circuit 21.